(1) Field of the Invention
The invention relates to voltage controlled oscillator circuits, and more particularly, to enhanced architectures of VCOs with a single inductor (VCO-1L).
(2) Description of the Prior Art
All of today's wireless communication systems utilize voltage controlled oscillator (VCO) circuits. Among them are base stations and mobile terminals/mobile phones and current communication devices, such as radios, etc. Besides lower power consumption, higher output amplitudes, broader tuning range, and cleaner spectrum, a lower phase noise is a most important parameter. It is a major challenge for the designer of VCOs to optimize all the key parameters, especially enhanced phase noise, of a VCO.
The initial topology of a differential one-inductor VCO (VCO-1L) has been introduced in several publications and gained popularity mostly due the publication of Jan Craninckx and Michel S. J. Steyaert (A Fully Integrated CMOS DCS-1800 Frequency Synthesizer, IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, December 1998, pp. 2054–2065).
The main advantages of said initial topology are related to the simple high-gain architecture, which is operational on almost any Si-process where standard quality transistors having complimentary polarity are available.
Throughout the patent applications the same markers have been used (e.g. M1, M2, M3, etc) in the drawings and correspondent in this document to signify in an architectural sense identical components of the circuits shown.
A principal schematic of said circuit is presented in FIG. 1 prior art having a N-MOS current mirror CM0 based on the N-MOS transistor M0, or, as shown in FIG. 2 prior art, with a P-MOS current mirror CM01 based on the P-MOS transistor M01. The power supply is noted by Vdd and differential output can be taken from the single ended left-output L and right-output R. The principle of operation of both variations is similar but the performance with respect to the frequency Instability measured by phase-noise is not exactly the same.
As shown in FIG. 1 the N-MOS transistors M1 and M2 form the lower layer of the gain providing structure, while the P-MOS transistors M3 and M4 form the upper layer. The parallel resonance LC-tank L0-C0 is connected between said lower layer and said upper layer determining mainly the frequency of oscillation. Usually, but not limited to, the frequency of oscillation is controlled by some varactors which constitute the controllable part of the capacitance of the capacitor C0.
The circuit is oscillating in a cross-manner: when transistors M1 and M3 are heading toward opening up, the transistors M2 and M4 are going to a closing down.
While the current mirror CM0 of FIG. 1 prior art is built in N-MOS technology, the current mirror CMO1 of FIG. 2 prior art is built using P-MOS technology. With the exception of the difference in the current mirrors CM0 resp. CM01 the structure of the circuits shown in FIG. 1 prior art and in FIG. 2 prior art is identical.
The timing of the process and indeed the stability of this timing are determined by the quality factor of the parallel resonance LC-tank formed by L0 and C0 in FIG. 1 prior art and in FIG. 2 prior art and the pick-to-pick amplitude on it. Thus, the instability of the amplitude and the frequency are caused by the other components in the circuit, which compensate the energy losses in the tank in order to keep the oscillations continuous.
The current mirrors CM0 resp. CM01 shown in FIG. 1 prior art resp. FIG. 2 prior art provide current stabilization of the total differential current throughout the circuit.
Different design strategies are applied for those two versions shown in FIG. 1 prior art and in FIG. 2 prior art of this topology, because the noise inside of the N-MOS and P-MOS transistors is different enough in nature and frequency components of said transistors, because the noise depends from the geometry and sizes of said transistors, and also because the major source of the noise in this architecture stems from the current mirrors CM0 resp. CM01. Slight preferences to the version with P-MOS mirror exist compared to the version with a N-MOS mirror.
U.S. Pat. No. 6,486,744 (to Cann) shows a low phase noise voltage-controlled oscillator (VCO) and method. The VCO comprises a negative resistance generator and a resonator that reduces VCO phase noise. In one embodiment, the VCO comprises a negative resistance generator and a resonator structure that reduces VCO phase noise. The VCO uses the reflection properties of the resonator. An advantage of one embodiment of the VCO is its relatively low cost of manufacture compared to other VCOs. Another advantage of one embodiment of the VCO is its lower phase noise compared to conventional microstrip resonators. In one embodiment, low phase noise performance is achieved by tuning the outside fingers of an interdigital filter resonator in the VCO and configuring suitable physical dimensions of the resonator. One aspect of the invention relates to a voltage-controlled oscillator comprising a resonator and a negative resistance generator. The resonator comprises a three-finger interdigital filter and a plurality of varactors. A first varactor is coupled to a first finger of the interdigital filter and a ground terminal. A second varactor is coupled to a third finger of the interdigital filter and a ground terminal. A second finger of the interdigital filter is coupled to a ground terminal. The first and second varactors are configured to alter a resonant frequency of the interdigital filter to a desired frequency in response to a tuning voltage applied to the resonator. The negative resistance generator is coupled to the resonator. The negative resistance generator is configured to receive a first signal with a particular frequency from the resonator. The negative resistance generator is configured to output a second signal with a substantially similar frequency and a higher amplitude compared to the first signal.
U.S. Pat. No. 6,353,368 (to Iravani) discloses a low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO output signal. The frequency to voltage converter converts a frequency of the VCO output signal into a corresponding voltage output. The voltage output is coupled to control the bias circuit. The VCO cell includes a current source coupled to the bias circuit such that the voltage output from the voltage a current converter provides negative feedback to the VCO cell via the current source. The negative feedback, in turn, reduces the phase noise on the VCO output signal.
U.S. Pat. No. 6,181,216 (to Waight) discloses an oscillator using a Field-Effect Transistor (FET) in a Colpitts configuration. The circuit has a resistor from source to ground. Also connected to the source are two capacitors, one between the source and ground while the other is from source to gate. These capacitors provide a phase-shifted feedback signal to the gate. Also connected to the gate is a varactor tank, which has a voltage variable reactance that is used to tune the oscillation to the desired frequency. Between the drain of the FET and the supply voltage is a resistor-capacitor network. Between two series resistors a shunt capacitor is added to minimize local oscillator leakage onto the Vdd line. The resistor network also provides impedance for the Pre-Scalar output, which is simply a connection to the drain of the FET. The pre-scalar output is used to provide a reference signal to the phase-locked loop, which generates the correction voltage to the oscillator's VCO input. It is at the pre-scalar output that a filter network is added to reduce the base-band noise from the Vdd line. By adding a shunt network, consisting of a small inductor and a low ESR capacitor, the supply noise is filtered without reducing the voltage or current supplied to the oscillator. The inductor removes the shunt capacitance at the oscillation frequency, avoiding any reduction in signal to the phase-locked loop circuit. The low ESR capacitor works with the resistance on-chip between the Vdd line and the drain to reduce the low frequency noise present at the FET's drain. This reduction in low-frequency noise results in improved phase noise performance without degrading any other circuit parameters.